A Current-Steering DAC Architecture with Novel Switching Scheme for GPON Burst-Mode Laser Drivers

This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 μm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binaryweighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below ± 0.5 LSB and that the settling time after the output current mirror is below 12 ns. Although the proposed IDAC architecture was designed for a BMLD chip, the design concept is generic and can be applied for developing other monotonic high-speed current-mode DACs. key words: current steering digital-to-analog converter, DNL, GPON, cascade current mirror, BiCMOS